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september 2013 doc id 15162 rev 4 1/47 1 l99dz70xp door actuator driver features one full bridge for 6 a load (r on = 150 m ) two half bridges for 3 a load (r on = 300 m ) two half bridges for 0.75 a load (r on = 1600 m ) one highside driver for 6 a load (r on =90m ) two configurable highside drivers for up to 1.5 a load (r on =500m ) or 0.4 a (r on = 1800 m ) two highside drivers for 0.5 a load (r on = 1600 m ) programmable softstart function to drive loads with higher inrush currents as current limitation value very low current consumption in standby mode (i s <6a typ; t j 85 c; i cc < 5 a typ; t j 85 c) current monitor output for all highside drivers device contains temperature warning and protection openload detection for all outputs over-current protection for all otputs separated half bridges for door lock motor pwm control of all outputs charge pump output for reverse polarity protection stm standard serial peripheral interface (st- spi 3.0) control block for electrochromic element applications door actuator driver with 6 bridges for double door lock control, mirror fold and mirror axis control, highside driver for mirror defroster, bulbs and leds (replacement for l9950). control block with external mos transistor for charging / discharging of electrochromic glass. description the l99dz70xp is a microcontroller driven multifunctional door actuator driver for automotive applications. up to five dc motors and five grounded resistive loads can be driven with six half bridges and five highside drivers. an electrochromic mirror glass can be controlled using the integrated spi-driven module in conjunction with an external mos transistor. the integrated spi controls all operating modes (forward, reverse, brake and high impedance). also all diagnostic information is available via spi read. powersso-36 table 1. device summary package order codes tube tape and reel powersso-36 l99dz70xp L99DZ70XPTR www.st.com
contents l99dz70xp 2/47 doc id 15162 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.4.1 outputs out1 - out11, ecv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 spi - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 dual power supply: vs and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 wake up and active mode / standby mode . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 overvoltage and undervoltage detection at v s . . . . . . . . . . . . . . . . . . . . 25 3.6 overvoltage and undervoltage detection at v cc . . . . . . . . . . . . . . . . . . . 25 3.7 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25 3.8 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10 over-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 pwm inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 programmable soft-start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 controller for electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.1 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.2 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
l99dz70xp contents doc id 15162 rev 4 3/47 4.1.3 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.4 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.5 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.1 operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 spi - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4 control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5 status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.7 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 powersso-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 powersso-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables l99dz70xp 4/47 doc id 15162 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. current monitor output cm / pwm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. charge pump output cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11. on-resistance and switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 12. current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. inputs: csn, clk, pwm1/2 and di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 16. sdi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17. do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 19. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 20. spi frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 24. rom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 25. control register 0 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 26. control register 1 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 27. control register 2 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 28. control register 3 (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 29. status register 0 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 30. status register 1 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 31. status register 2 (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 32. configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 33. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 34. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
l99dz70xp list of figures doc id 15162 rev 4 5/47 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. electrochrome control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 4. spi - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5. spi - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. spi - do valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. spi - do enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. spi - driver turn on/off timing, minimum csn hi time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. example of programmable soft-start function for inductive loads . . . . . . . . . . . . . . . . . . . . 27 figure 10. write and read spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. global error flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 14. powersso-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
block diagram and pin description l99dz70xp 6/47 doc id 15162 rev 4 1 block diagram and pin description figure 1. block diagram table 2. pin definition and functions pin symbol function 1, 18, 19, 36 gnd ground: reference potential. important: for the capability of driving the full current at the outputs all pins of gnd must be externally connected! 2, 35 out11 highside driver output 11. the output is built by a highside switch and is intended for resistive loads, therefore the internal reverse diode from gnd to the output is missing. for esd reason a diode to gnd is present, but the energy which can be dissipated is limited. the highside driver is a power dmos transistor with an internal parasitic reverse diode from the output to vs (bulk-drain-diode). the output is over-current protected. important: for the capability of driving the full current at the outputs both pins of out11 must be externally connected! driver interface & diagnostic m spi interface charge pump cm/pwm2 csn clk do di vs vcc vcc v bat spc560d gnd 1k cm mux pwm1 1k 1k 1k 1k 1k 100k 10k 100f 100nf l99pm62gxp cp m m m standby ec glass control block 6bit spi controlled progr. bulb or led mode out1 out2 out3 out4 out5 out6 out9 out7 out8 out11 st spi m 300 m 1600 m 1600 m 150 m 150 m 300 m 1600 m 1600 m 1600 m 90 m 1800 / 500 ecdr (vs) 10 watt 10 watt ecv (vs) out10 std18nf03l std18nf03l m 1800 / 500 all components to be placed together as close as possible 5 nf 100 nf m
l99dz70xp block diagram and pin description doc id 15162 rev 4 7/47 3 4 5 out1, out2, out3 halfbridge outputs 1,2,3. the output is built by a highside and a lowside switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: highside driver from output to vs, lowside driver from gnd to output). this output is over-current protected. 6, 7, 14, 15, 23, 24, 28, 29 v s power supply voltage (external reverse protection required). for this input a ceramic capacitor as close as possible to gnd is recommended. important: for the capability of driving the full current at the outputs all pins of vs must be externally connected! 8di serial data input. the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 24 bit control word and the most significant bit (msb, bit 23) is transferred first. 9 cm/ pwm2 current monitor output/pwm2 input. depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding highside driver with a ratio of 1/10.000 or 1/2000. this pin is bidirectional. the microcontroller can overdrive the current monitor signal to provide a second pwm input for the outputs out5, out8 and out10. 10 csn chip select not input / testmode. this input is low active and requires cmos logic levels. the serial data transfer between l99dz70 and the microcontroller is enabled by pulling the input csn to low level. 11 do serial data output. the diagnosis data is available via the spi and this tristate-output. the output will remain in tristate, if the chip is not selected by the input csn (csn = high) 12 vcc supply voltage. for this input a ceramic capacitor as close as possible to gnd is recommended. 13 clk serial clock input. this input controls the internal shift register of the spi and requires cmos logic levels. 16,17 20,21 22 out4, out5, out6 halfbridge outputs 4,5,6: see out1 (pin 3). important: for the capability of driving the full current at the outputs both pins of out4 (out5, respectively) must be externally connected! 25 ecdr electrocromic driver output. if the electrochrome mode is selected this pin is used to control the gate of an external mosfet, otherwise it remains in high-impedance state. note: it is possible to connect the pin to vs as in l9950/53/54 applications, as long as the electrochome mode is not enabled via spi. 26 cp charge pump output. this output is provided to drive the gate of an external n-channel power mos used for reverse polarity protection (see figure 1. ). table 2. pin definition and functions (continued) pin symbol function
block diagram and pin description l99dz70xp 8/47 doc id 15162 rev 4 27 pwm1 pwm1 input. this input signal can be used to control the drivers out1-4, out6-7, out9 and out11 and ecv by an external pwm signal. 30 31 out7, out8, highside driver outputs 7,8: see out9. by selection of one of the 2 power dmos at same output is it possible to supply a bulb with low on-resistance or a led with higher on-resistance in a different application. 32 ecv electrochrome voltage input and lowside driver output. this input senses voltage in electrocrome mode for charge monitoring. the lowside switch provides a fast discharge of electrocromic mirror and can be used 'stand alone' as lowside switch beside electrocromic mode. 33 out9 highside driver output 9. the output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from gnd to the output is missing. for esd reason a diode to gnd is present but the energy which can be dissipated is limited. the highside driver is a power dmos transistor with an internal parasitic reverse diode from the output to vs (bulk-drain-diode). the output is over-current and open load protected. 34 out10 highside driver output 10: see out9. important: beside the bit10 in control register 1 this output can be switched on setting bit1 for electrocromic control mode with higher priority. table 2. pin definition and functions (continued) pin symbol function
l99dz70xp block diagram and pin description doc id 15162 rev 4 9/47 figure 2. configuration diagram (top view) note: all pins with the same name must be externally connected. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd out11 out1 out2 out3 vs vs di cm / pwm2 csn do vcc clk vs vs out4 out4 gnd gnd out5 out5 out6 vs vs ecdr cp pwm1 vs vs out7 out8 ecv out9 out10 out11 gnd powersso-36
electrical specifications l99dz70xp 10/47 doc id 15162 rev 4 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality document. 2.2 esd protection table 3. absolute maximum ratings symbol parameter value unit vs dc supply voltage -0.3...28 v single pulse t max < 400 ms 40 v vcc stabilized supply voltage, logic supply -0.3 to 5.5 v v di , v do, v clk, v csn, v pwm digital input / output voltage -0.3 to v cc + 0.3 v v cm current monitor output -0.3 to v cc + 0.3 v v cp charge pump output -25 .. v s + 11 v v outn, ecdr, ecv static output voltage (n= 1 to 11) -0.3 to v s + 0.3 v i out,2,3,9,10, ecv output current 1.25 a i out1,6,7,8, output current 5 a i out4,5,11 output current 10 a table 4. esd protection parameter value unit all pins 2 (1) 1. hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a. kv output pins: out1 - out6, ecv 4 (2) 2. hbm with all unzapped pins grounded. kv
l99dz70xp electrical specifications doc id 15162 rev 4 11/47 2.3 thermal data 2.4 electrical characteristics v s = 8 to 16v, v cc = 4.5 to 5.3v, t j = - 40 to 150c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 5. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c table 6. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t jtw on temperature warning threshold junction temperature t j 130 150 c t jsd on thermal shutdown threshold junction temperature t j increasing 170 c t jsd off thermal shutdown threshold junction temperature t j decreasing 150 c t jsd hys thermal shutdown hysteresis 5 k table 7. supply item symbol parameter test condition min. typ. max. unit 7.1 vs operating voltage range 728v 7.2 i s v s dc supply current v s =16v, v cc =5.3v active mode out1 - out11, ecv, ecdr floating 720ma 7.3 v s quiescent supply current v s =16v, v cc =0v standby mode out1 - out11, ecv, ecdr floating t test = -40c, 25c 412 a 7.4 (1) t test = 85c 6 25
electrical specifications l99dz70xp 12/47 doc id 15162 rev 4 7.5 i cc v cc dc supply current v s =16v, v cc =5.3v csn = v cc , active mode out1 - out11, ecv, ecdr floating 13ma 7.6 (2) v cc quiescent supply current v s =16v, v cc =5.3v csn =v cc standby mode out1 - out11, ecv, ecdr floating t test = -40c, 25c 36 a 7.7 (1) t test = 85c 5 10 1. this parameter is guaranteed by design. 2. cm/ pwm 2 = v cc or 0 v. table 8. overvoltage and under voltage detection item symbol parameter test condition min. typ. max. unit 8.1 v suv on v s uv-threshold voltage v s increasing 5.6 7.2 v 8.2 v suv off v s uv-threshold voltage v s decreasing 5.2 6.1 v 8.3 v suv hyst v s uv-hysteresis v suv on - v suv off 0.5 v 8.4 v sov off v s ov-threshold voltage v s increasing 18 24.5 v 8.5 v sov on v s ov-threshold voltage v s decreasing 17.5 23.5 v 8.6 v sov hyst v s ov-hysteresis v sov off - v sov on 1v 8.7 v por off power-on-reset threshold v cc increasing 2.9 v 8.8 v por on power-on-reset threshold v cc decreasing 2.0 v 8.9 v por hyst power-on-reset hysteresis v por off - v por on 0.11 v table 9. current monitor output cm / pwm 2 item symbol parameter test condition min. typ. max unit 9.1 v cm functional voltage range 0v cc -1v v 9.2 i cm,r current monitor output ratio: i cm /i out1,4,5,6,11 and 7,8 (low on-resistance) 0v <= v cm <= 4v v cc =5v 9.3 i cm /i out2,3,9,10 and 7,8 (high on-resistance) table 7. supply (continued) item symbol parameter test condition min. typ. max. unit 1 10.000 ----------------- - 1 2000 ------------ - ,
l99dz70xp electrical specifications doc id 15162 rev 4 13/47 2.4.1 outputs out1 - out11, ecv 9.4 i cm acc current monitor accuracy acci cmout1,4,5,6, 11and 7, 8 (low on-res.) v cm <= 3.8v, v cc = 5v i out,min = 500ma i out4,5,11max = 5.9a i out1,6 max = 2.9a i out7,8 max = 1.3a 4% + 1%fs (1) 8% + 2%fs (1) 9.5 acci cmout2,3,9,10, and 7, 8 (high on-res.) i out,min = 100 ma i out2,3 max = 0.6 a i out9,10max = 0.4 a i out8 max = 0.3 a 1. fs (full scale)= i outmax * i cm,r . table 10. charge pump output cp item symbol parameter test condition min. typ. max unit 10.1 v cp charge pump output voltage v s = 8v, i cp = -60a v s +6 v s +13 v 10.2 v s = 10v, i cp = -80a v s +8 v s +13 v 10.3 v s >=12v, i cp = -100a v s +10 v s +13 v 10.4 i cp charge pump output current v cp = v s +10v, v s =13.5v 95 150 300 a table 9. current monitor output cm / pwm 2 (continued) item symbol parameter test condition min. typ. max unit table 11. on-resistance and switching times item symbol parameter test condition min. typ. max. unit 11.1 r on out1, r on out6 on-resistance to supply or gnd v s =13.5v, t j =25c, i out1,6 =1.5a 300 400 m 11.2 v s =13.5v, t j = 125 c, i out1,6 =1.5a 450 600 m 11.3 r on out2, r on out3 on-resistance to supply or gnd v s =13.5v, t j =25c, i out2,3 = 0.4a 1600 2200 m 11.4 v s =13.5v, t j = 125 c, i out2,3 =0.4a 2500 3400 m
electrical specifications l99dz70xp 14/47 doc id 15162 rev 4 11.5 r on out4, r on out5 on-resistance to supply or gnd v s =13.5v, t j =25c, i out4,5 =3.0a 150 200 m 11.6 v s =13.5v, t j = 125 c, i out4,5 =3.0a 225 300 m 11.7 r on out9, r on out10 on-resistance to supply v s =13.5v, t j =25c, i out9,10 =-0.4a 1600 2200 m 11.8 v s =13.5v, t j = 125 c, i out9,10 =-0.4a 2500 3400 m 11.9 r on out11 on-resistance to supply v s =13.5v, t j =25c, i out11 =-3.0a 90 130 m 11.10 v s =13.5v, t j = 125 c, i out11 =-3.0a 130 180 m 11.11 r on out7 r on out8 on-resistance to supply in low mode (control register 1 bits 12 to15: 0101) v s =13.5v, t j =25c, i out7,8 =-0.8a 500 700 m 11.12 v s =13.5v, t j = 125 c, i out7,8 =-0.8a 700 950 m 11.13 on-resistance to supply in high mode (control register 1 bits 12 to15: 1010) v s =13.5v, t j =25c, i out7,8 =-0.2a 1800 2400 m 11.14 v s =13.5v, t j = 125 c, i out7,8 =-0.2a 2500 3400 m 11.15 r on ecv on-resistance to gnd v s =13.5v, t j =25c, i outecv =+0.4a 1600 2200 m 11.16 v s =13.5v, t j = 125 c, i outecv =+0.4a 2500 3400 m 11.17 i qlh switched-off output current highside drivers of out1-6, 8-11 v out = 0v, standby mode -5 -2 a 11.18 v out = 0v, active mode -10 -7 a table 11. on-resistance and switching times (continued) item symbol parameter test condition min. typ. max. unit
l99dz70xp electrical specifications doc id 15162 rev 4 15/47 11.19 i qlh7,8 switched-off output current highside drivers of out7-8 v out = 0v, standby mode -5 -2 a 11.20 v out = 0v, active mode -15 -10 a 11.21 i qll switched-off output current lowside drivers of out1-6 v out = v s , standby mode 80 120 a 11.22 v out = 0v, active mode -10 -7 a 11.23 switched-off output current lowside drivers of ecv v out = v s , standby mode -15 15 a 11.24 v out = v s , active mode -10 10 a 11.25 t d on h output delay time, highside driver on (out x except out 7,8 ) v s =13.5v, v cc =5v (1)(2)(3) 20 40 80 s 11.26 output delay time, highside driver on (out 7,8 in high r dson mode) 15 35 60 s 11.27 output delay time, highside driver on (out 7,8 in low r dson mode) 10 35 80 s 11.28 t d off h output delay time, highside driver off (out 1, 4, 5, 6, 11 ) v s =13.5v, v cc =5v (1)(2)(3) 60 150 200 s 11.29 output delay time, highside driver off (out 2,3,7, high/low r dson , 8 high/low r dson , 9, 10 ) 40 70 100 s 11.30 t d on l output delay time, lowside driver on v s =13.5v, v cc =5v, corresponding highside driver is not active (1)(2)(3) 15 30 70 s 11.31 t d off l 1-6 output delay time, lowside driver out 1-6 off v s =13.5v, v cc =5v (1)(2)(3) 40 150 300 s 11.32 t d off l ecv output delay time, lowside driver ecv off 15 45 80 s table 11. on-resistance and switching times (continued) item symbol parameter test condition min. typ. max. unit
electrical specifications l99dz70xp 16/47 doc id 15162 rev 4 11.33 t d hl cross current protection time t cc onls_offhs - t d offh (4) 50 200 400 s 11.34 t d lh t cc onhs_offls - t d offl (4) 11.35 dv out /dt on/off slew rate of outx v s =13.5v, v cc =5v (1)(2)(3 ) ) 0.1 0.2 0.6 v/s 1. rload = 16 at out1, 6 and 7,8 in low on-resistance mode. 2. rload = 4 at out4, 5 and 11. 3. rload = 64 at out2, 3, 9, 10, ecv and 7, 8 in high on-resistance mode. 4. t cc is the switch-on delay time if complement in half bridge has to switch-off. table 12. current monitoring item symbol parameter test condition min. typ. max. unit 12.1 |i oc1 |, |i oc6 | over-current threshold to supply or gnd v s =13.5v, v cc =5v, sink and source 35a 12.2 |i oc2 |, |i oc3 | 0.75 1.25 a 12.3 |i oc4 |, |i oc5 | 610a 12.4 |i oc9 |, |i oc10 | over-current threshold to supply v s =13.5v, v cc = 5 v, source 0.5 1.0 a 12.5 |i oc11 | 6 10 a 12.6 |i oc7 |, |i oc8 | over-current threshold to supply in low on-resistance mode v s =13.5v, v cc =5v, source, control register 1 bits 12 to 15: 0101 1.5 2.5 a 12.7 over-current threshold to supply in high on-resistance mode v s =13.5v, v cc =5v, source, control register 1 bits 12 to 15: 1010 0.35 0.65 a 12.8 |i ocecv | output current limitation to gnd v s =13.5v, v cc = 5 v, source 0.75 1.25 a 12.9 t foc filter time of over-current signal duration of over-current condition to set the status bit 10 55 100 s 12.10 f rec0 recovery frequency for oc recovery duty cycle bit= 0 14khz 12.11 f rec1 recovery frequency for oc recovery duty cycle bit= 1 26khz table 11. on-resistance and switching times (continued) item symbol parameter test condition min. typ. max. unit
l99dz70xp electrical specifications doc id 15162 rev 4 17/47 12.12 ii old1 i, ii old6 i under-current threshold to supply or gnd v s =13.5v, v cc =5v, sink and source 10 30 80 ma 12.13 ii old2 i, ii old3 i 10 20 30 ma 12.14 ii old4 i, ii old5 i 60 150 300 ma 12.15 ii old9 i, ii old10 i under-current threshold to supply v s =13.5v, v cc = 5 v, source 51015ma 12.16 ii old11 i 30 150 300 ma 12.17 ii old7 i, ii old8 i under-current threshold to supply in low on-resistance mode 15 40 60 ma 12.18 under-current threshold to supply in high on-resistance mode 51015ma 12.19 ii oldecv i under-current threshold to gnd v s =13.5v, vcc = 5v, sink 10 20 30 ma 12.20 t fol filter time of under-current duration of under- current condition to set the status bit 0.5 3 ms table 13. electrochrome control item symbol parameter test condition min. typ. max. unit 13.1 v ctrlmax maximum ec-control voltage bit 0= 1 control reg. 2 (1) 1.4 1.6 v 13.2 bit 0= 0 control reg. 2 (1) 1.12 1.28 v 13.3 dnl differential non linearity -1 1 lsb (2) 13.4 idv ecv i voltage deviation between target and ecv dv ecv =v target (3) -v ecv ii ecdr i < 1a -5% -1 lsb (3) +5% +1 lsb (3) mv 13.5 dv ecvnr difference voltage between target and ecv sets flag if v ecv is: below it dv ecv = v target - v ecv toggle bit 1=1 status reg. 2 120 mv 13.6 dv ecvhi above it toggle bit 0= 1 status reg. 3 -120 mv 13.7 v ecdrmin_high output voltage range i ecdr = -10 a 4.5 5.5 v 13.8 v ecdrmax_low i ecdr = 10 a 0 0.7 v table 12. current monitoring (continued) item symbol parameter test condition min. typ. max. unit
electrical specifications l99dz70xp 18/47 doc id 15162 rev 4 figure 3. electrochrome control block diagram 2.5 spi - electrical characteristics v s = 8 to 16v, v cc = 4.5 to 5.5v, t j = - 40 to 150c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 13.9 i ecdr current into ecdr v target >v ecv + 500mv, v ecdr = 3.5v -100 -10 a 13.10 v target < v ecv - 500mv, v ecdr = 1.0v; v target =1 lsb; v ecv =0.5v 10 100 a 13.11 r ecdrdis pulldown resistance at ecdr in fast discharge mode v ecdr = 0.7v ; cntrl reg 1: bit 8 and bit 1 = 1, all other bits = 0 5k 13.12 i qecdr quiescent current v ecdr = v s ; cntrl. reg 1 bit 1 = 0 1a 1. bit 7 to 2 = ?1? control register 1: ecv voltage, where ii ecdr can change sign. 2. 1 lsb (least significant bit)= 23.8 mv. 3. v target is set by bit 7 to 2 of control register 1 and bit 0 of control register 2; tested for each individual bit. table 13. electrochrome control (continued) item symbol parameter test condition min. typ. max. unit d a c
l99dz70xp electrical specifications doc id 15162 rev 4 19/47 table 14. delay time from standby to active mode item symbol parameter test condition min. typ. max. unit 14.1 t set delay time switching from standby to active mode. time until output drivers are enabled after csn going to high and set bit 0=1 of control register 0. 256 300 s table 15. inputs: csn, clk, pwm1/2 and di item symbol parameter test condition min. typ. max. unit 15.1 v inl input low level v cc = 5v 0.3* vcc v 15.2 v inh input high level v cc = 5v 0.7* vcc v 15.3 v in hyst input hysteresis v cc = 5v 500 mv 15.4 r csn in csn pull up resistor v cc = 5v 0v electrical specifications l99dz70xp 20/47 doc id 15162 rev 4 16.8 t r in rise time of input signal di, clk, csn v cc = 5v 100 ns 16.9 t f in fall time of input signal di, clk, csn v cc = 5v 100 ns 1. di timing parameters tested in production by a passed / failed test: tj= -40c / +25c: spi communication @ 2mhz. tj= +125c spi communication @ 1.25 mhz. table 17. do item symbol parameter test condition min. typ. max. unit 17.1 v dol output low level i do = -5 ma 0.2v cc v 17.2 v doh output high level i do = 5 ma 0.8 v cc v 17.3 i dolk tristate leakage current v csn = v cc , 0v < v do < v cc -10 10 a 17.4 c do (1) 1. value of input capacity is not measured in production test. parameter guaranteed by design. tristate input capacitance v csn = v cc , 0v < v cc < 5.3v 10 pf table 18. do timing item symbol parameter test condition min. typ. max. unit 18.1 t r do do rise time c do = 100 pf 80 140 ns 18.2 t f do do fall time c do = 100 pf 50 100 ns 18.3 t en do tri l do enable time from tristate to low level c do = 100 pf, i load = 1ma pull-up load to v cc 100 250 ns 18.4 t dis do l tri do disable time from low level to tristate c do = 100 pf, i load = 4 ma pull-up load to v cc 380 450 ns 18.5 t en do tri h do enable time from tristate to high level c do =100 pf, i load = -1ma pull-down load to gnd 100 250 ns 18.6 t dis do h tri do disable time from high level to tristate c do = 100 pf, i load = -4ma pull-down load to gnd 380 450 ns 18.7 t d do do delay time v do < 0.3 v cc , v do > 0.7 v cc , c do = 100 pf 50 250 ns table 16. sdi timing (continued) (1) item symbol parameter test condition min. typ. max. unit
l99dz70xp electrical specifications doc id 15162 rev 4 21/47 figure 4. spi - transfer timing diagram figure 5. spi - input timing table 19. csn timing item symbol parameter test condition min. typ. max. unit 19.1 t csn_hi,stb mimimum csn hi time, switching from standby mode transfer of spi- command to input register 20 50 s 19.2 t csn_hi,min minimum csn hi time, active mode transfer of spi- command to input register 24s 1234567 0 01 1234567 0 1234567 0 01 01 csn clk di do input data register csn high to low: do enabled time di: data will be accepted on the rising edge of clk signal time time time time do: data will change on the falling edge of clk signal fault bit csn low to high: actual data is transfered to output power switches old data new data 23 22 21 20 19 18 23 22 21 20 19 18 23 22 21 20 19 18 x x x x x x 1234567 0 01 1234567 0 1234567 0 01 1234567 0 1234567 0 01 01 csn clk di do input data register csn high to low: do enabled time di: data will be accepted on the rising edge of clk signal time time time time do: data will change on the falling edge of clk signal fault bit csn low to high: actual data is transfered to output power switches old data new data 1234567 0 01 01 csn clk di do input data register csn high to low: do enabled time di: data will be accepted on the rising edge of clk signal time time time time do: data will change on the falling edge of clk signal fault bit csn low to high: actual data is transfered to output power switches old data new data 23 22 21 20 19 18 23 22 21 20 19 18 23 22 21 20 19 18 x x x x x x 0.8 vcc 0.8 vcc 0.8 vcc 0.2 vcc 0.2 vcc 0.2 vcc valid va l id csn clk di t set csn t clkh t se t clk t clkl t hold di t set di
electrical specifications l99dz70xp 22/47 doc id 15162 rev 4 figure 6. spi - do valid data delay time and valid time figure 7. spi - do enable and disable time 0 . 8 v cc 0 . 8 v cc 0 . 8 v cc 0 . 2 v c c 0 . 2 v c c 0 . 2 v cc c l k do ( l o w t o h i g h ) do (high to lo w ) 0 . 5 v cc t r in t r d o t f do t d do t f i n csn t f in r in t do do en do tri l t t dis do l tri 50% 0.8 vcc 0.2 vcc 50% 50% en do tri h t t dis do h tri c = 100 pf l c = 100 pf l pull-up load to vcc pull-down load to gnd
l99dz70xp electrical specifications doc id 15162 rev 4 23/47 figure 8. spi - driver turn on/of f timing, minimum csn hi time c s n don t 2 0 % 8 0 % t r i n f i n t o f f t d o f f t off s t ate o n s t a t e o f f s t a t e on s t a t e o n t o u t p u t c u r r e n t o f a d r i v e r 5 0 % 5 0 % 8 0 % 2 0 % 20 % 80 % 5 0 % o u t p u t c u r r e n t o f a d r i v e r csn lo w t o h igh : d ata f r o m s h i f t registe r is t r ansfe r r e d t o outpu t po w e r s w i t c h es t csn_hi,min output voltage of a driver output voltage of a driver
application information l99dz70xp 24/47 doc id 15162 rev 4 3 application information 3.1 dual power supply: v s and v cc the power supply voltage v s supplies the half bridges and the highside drivers. an internal charge-pump is used to drive the highside switches. the logic supply voltage v cc is used for the logic part and the spi of the device. due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. 3.2 wake up and active mode / standby mode after power up of vs and vcc the device operates in standby-mode. pulling the signal csn to low level wakes the device up and the analog part will be activated (active mode). after at least 10s, the first spi communication is valid and bit 0 of the control register 0 can be used to set the en-mode. if bit 0 is not set to 1, the device doesn't remain in the active mode. after at least 256s all latched data will be cleared and the inputs and outputs are switched to high impedance. in standby mode the current at v s (v cc ) is less than 6 a (5 a) for csn = high (do in tristate). 3.3 charge pump in standby mode the chargepump is turned off. after enabling the device by spi command (bit0=1 control register 0) the oscillator starts and the voltage begins to increase. the output drivers are enabled after at least 256 s after csn went to high. 3.4 diagnostic functions all diagnostic functions (over/under-current, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered. the condition has to be valid for at least 32 s (open load: 1ms) before the corresponding status bit in the status registers is set. the filters are used to improve the noise immunity of the device. the under-current and temperature warning functions are intended for information purpose and will not change the state of the output drivers. on contrary, the over-current condition disables the corresponding driver and thermal shutdown disables all drivers. without setting the over- current recovery bits in the input data register, the microcontroller has to clear the over- current status bits to reactivate the corresponding drivers.
l99dz70xp application information doc id 15162 rev 4 25/47 3.5 overvoltage and undervoltage detection at v s if the power supply voltage vs rises above the overvoltage threshold v sov off (typical 21 v), the outputs out1 to out11, ecdr and ecv are switched to high impedance state to protect the load. when the voltage vs drops below the undervoltage threshold v suv off (uv-switch-off voltage), the output stages are switched to high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). if the supply voltage v s recovers (control register 3: bit 4=0) to normal operating voltage then the outputs stages return to the programmed state. if the undervoltage/overvoltage recovery disable bit is set (control register 3: bit 4=1), the automatic turn-on of the drivers is deactivated. the microcontroller needs to clear the status bits to reactivate the drivers. it is recommended to set bit1 control register 3 to avoid a possible high current oscillation in case of a shorted output to gnd and low battery voltage. 3.6 overvoltage and undervoltage detection at v cc in case of power-on (vcc increases from undervoltage to v por off = 2.9 v) the circuit is initialized by an internally generated power-on-reset (por). if the voltage vcc decreases below the minimum threshold (v por on = 2.0 v), the outputs are switched to tristate (high impedance) and the status registers are cleared. 3.7 temperature warning and thermal shutdown if the junction temperature rises above t j tw , a temperature warning flag is set after at least 32 s and it can be read via the spi. if the junction temperature increases above the second threshold t jsd , the thermal shutdown bit is set and the power dmos transistors of all output stages are switched off to protect the device after at least 32 s. the temperature warning and thermal shutdown flags are latched and the bits must be cleared by the microcontroller. this is possible only if the temperature has decreased below trigger temperature. if the thermal shutdown bit has been cleared the output stages are reactivated. 3.8 inductive loads each half bridge is built by internally connected highside and lowside power dmos transistors. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs out1 to out6 without external free-wheeling diodes. the highside drivers out7 to out11 are intended to drive resistive loads. therefore only a limited energy (e<1mj) can be dissipated by the internal esd-diodes in freewheeling condition. for inductive loads (l>100h) an external free-wheeling diode connected between gnd and the corresponding output is required. the low side driver at ecv does not have a freewheel diode built into the device.
application information l99dz70xp 26/47 doc id 15162 rev 4 3.9 open load detection the open load detection monitors the load current in each activated output stage. if the load current is below the open load detection threshold for at least 1 ms (t dol ) the corresponding open load bit is set in the status register. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 3.10 over-load detection in case of an over-current condition a flag is set in the status register in the same way as during open load detection. if the over-current signal is valid for at least t isc (typ) = 55 s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. if the over-current recovery bit of the output is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver. 3.11 current monitor the current monitor output sources a current image at the current monitor output which has two fixed ratios of the instantaneous current of the selected highside driver. outputs with a resistance of 500 m and higher have a ratio of 1/2000 and those with a lower resistance of 1/10000. the signal at output cm is blanked after switching on the driver until correct settlement of the circuitry (at least for 64 s). the bits 0 to 3 of the control register 3 define which of the outputs are multiplexed to the current monitor output cm/pwm2. the current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. for example it can be used to detect the motor state (starting, free-running, stalled). moreover, it is possible to control the power of the defroster more precisely by measuring the load current. the current monitor output is bidirectional (pwm inputs). 3.12 pwm inputs each driver has a corresponding pwm enable bit, which can be programmed by the spi interface. if the pwm enable bit is set in control registers 2 or 3, the output is controlled by the logically and-combination of the pwm signal and the output control bit in control registers 0 and 1. the outputs out1-4, 6, 7, 9, out11 are controlled by the pwm1 input and the outputs out5, 8 and out10 are controlled by the bidirectional input cm/pmw2. for example, the two pwm inputs can be used to dim two lamps independently by external pwm signals. in case of switching off a high/low side switch in pwm mode a minimum off time of appr. (256 s ? td on + td off ) is predefined by the state machine, to avoid switching on the high/low side again during the negative slope. for a pwm frequency of 100hz this means the maximum duty cycle is about 98%. larger duty cycles can be realized by applying pulse skipping.
l99dz70xp application information doc id 15162 rev 4 27/47 3.13 cross-current protection the six half-brides of the device are cross-current protected by an internal delay time. if one driver (ls or hs) is turned off, the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. after the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behaviour it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct. 3.14 programmable soft-start function to drive loads with higher inrush current loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). each driver has a corresponding over-current recovery bit. if this bit is set, the device automatically switches the outputs on again after a programmable recovery time. the duty cycle in over-current condition can be programmed by the spi interface to about 12% or 25%. the pwm modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. the pwm frequency settles at 1.7khz and 3khz. the device itself cannot distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. for over-load detection the microcontroller can switch on the light bulbs by setting the over-current recovery bit for the first e.g. 50ms. after clearing the recovery bit the output will be automatically switched off, if the overload condition remains. this over-load detection procedure has to be followed in order make it possible to switch on the low-side driver of a bridge output, if the associated high-side driver has been used in recovery mode before. figure 9. example of programmable soft -start function for inductive loads
application information l99dz70xp 28/47 doc id 15162 rev 4 3.15 controller for electrochromic glass the voltage of an electrochromic element connected at pin ecv can be controlled to a target value, which is set by the bits 7 down to 2 of control register 1. setting bit 1 of control register 1 enables this function. an on-chip differential amplifier and an external mos source follower, with its gate connected to pin ecdr and which drives the electrochrome mirror voltage at pin ecv, form the control loop. the drain of the external mos transistor is supplied by out10. a diode from pin ecv (anode) to pin ecdr (cathode) has been placed on the chip to protect the external mos source follower. a capacitor of at least 5 nf has to be added to pin ecdr for loop-stability. the target voltage is binary coded with a full scale range of 1.5v. if bit 0 of control register 2 is set to '1', the maximum controller output voltage is clamped to 1.2v without changing the resolution of bits 7-2 of control register 1. when setting the target voltage to 0v and programming the ecvls driver to on-state, the voltage at pin ecv is pulled to ground by a 1.6 ohm low-side switch (fast discharge). the status of the voltage control loop is reported via spi. bit 0 in the status register 2 is set, if the voltage at pin ecv is higher, whereas bit 1 in the same status register is set, if the voltage at pin ecv is lower than the target value. both status bits are valid, if they are stable for at least 150 s. since out10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an over current detection, the control loop is switched off). in electrochrome mode out10 cannot be controlled by pwm mode. for ems reasons the loop capacitor at pin ecdr as well as the capacitor between ecv and gnd have to be placed to the respective pins as close as possible.
l99dz70xp functional description of the spi doc id 15162 rev 4 29/47 4 functional description of the spi 4.1 general description standard st-spi interface version 3.0. the spi communication is based on a serial peripheral interface interface structure using csn (chip select not), di (serial data in), do (serial data out/error) and clk (serial clock) signal lines. 4.1.1 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal wakes up the device and a serial communication can be started. the state when csn is going low until the rising edge of csn will be called a communication frame. 4.1.2 serial data in (di) the input pin is used to transfer data serially into the device. the data applied to the di will be sampled at the rising edge of the clk signal. 4.1.3 serial clock (clk) this input signal provides the timing of the serial interface. the data input (di) is latched at the rising edge of serial clock clk . the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. data on serial data out (do) is shifted out at the falling edge of the serial clock (clk). the serial clock clk must be active only during a frame (csn low). any other switching of clk close to any csn edge could generate set up/hold violations in the spi logic of the device. the clock monitor counts the number of clock pulses during a communication frame (while csn is low). if the number of clk pulses does not correspond to the frame width indicated in the (rom address 03h) the frame is ignored and the bit in the is set. note: due to this safety functionality, daisy chaining the spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. 4.1.4 serial data out (do) the data output driver is activated by a logical low level at the csn input and will go from high impedance to a low or high level depending on the global status bit 7 (global error flag). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out.
functional description of the spi l99dz70xp 30/47 doc id 15162 rev 4 4.1.5 spi communication flow at the beginning of each communication the master can read the contents of the register (rom address 03h) of the slave device. this 8-bit register indicates the spi frame length (24 bit) and the availability of additional features. each communication frame consists of a command byte which is followed by 2 data bytes. the data returned on do within the same frame always starts with the byte. it provides general status information about the device. it is followed by 2 data bytes (i. e. ? in-frame-response? ). for write cycles the byte is followed by the previous content of the addressed register. figure 10. write and read spi
l99dz70xp functional description of the spi doc id 15162 rev 4 31/47 ocx: operation code ax: address dx: data bit 4.2 command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation ( , , , ) and a 6 bit address. if less than 6 address bits are required, the remaining bits are unused but are reserved. 4.2.1 operation code definition the and operations allow access to the ram of the device. a operation is used to read a status register and subsequently clear its content. the allows access to the rom area which contains device related information such as , , and . table 20. spi frame command byte data byte data byte bit 23 22 212919181716151413121110 9 8 7 6543210 name oc1 oc0 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 21. operation code definition oc1 oc0 meaning 0 0 0 1 1 0 1 1
functional description of the spi l99dz70xp 32/47 doc id 15162 rev 4 4.3 global status byte description: gl_er : global error flag. failures of bits 0-6 are always linked to the global error flag. this flag is generated by an or combination of all failure events of the device. it is reflected via the do pin while csn is held low and no clock signal is available. the flag will remain as long as csn is low. this operation does not cause the communication error bit in the to be set. the signal tw bit3 and ol bit1can be masked. co_er : communication error. if the number of clock pulses within the previous frame is not 24 the frame is ignored and this bit is set. c_reset : chip reset. if a stuck at ?1? on input di during any spi frame occurs, or if a power on reset (vcc monitor) occurs. c_reset will be reset (?1?) with any spi command. when stk_reset_q is active (?0?), the gate drivers are switched off (resistive path to source). after a startup of the circuit the stk_reset_q is active because of the por pulse and the gate drivers are switched off. the gate drivers can only be activated after the stk_reset_q has been reset with a spi command. tsd : thermal shutdown due to an internal sensor. all the gate drivers and the charge pump must be switched off (resistive path to source). the tsd bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump. tw : thermal warning. this bit is maskable by configuration register. uov_oc : logical or among the filtered under-/over-voltage signals and over-current signals. ol : open load. logical or among the filtered under-current signals. this bit is maskable by configuration register. nr : not ready. after switching the device from standby mode to active mode an internal timer is started to allow chargepump to settle before the outputs can be activated. this bit is cleared automatically after start up time has finished. table 22. global status byte bit76543210 name gl_er co_er c_reset tsd tw uov_oc ol nr reset 0 0 1 0 0 0 0 0
l99dz70xp functional description of the spi doc id 15162 rev 4 33/47 figure 11. global error flag definition 4.4 address mapping table 23. ram memory map address name access content 00h control register 0 read/write enable of device and bridge control 01h control register 1 read/write high/low-side control and electrocrome block set up 02h control register 2 read/write bridge recovery mode and pwm set up and electrocrome block set up 03h control register 3 read/write highside recovery mode and pwm set up and current monitor selection 10h status register 0 read only bridge over-current diagnosis 11h status register 1 read only bridge open load (under-current) diagnosis 12h status register 2 read only open load (under-current) diagnosis, vs and electrocrome diagnosis 3fh configuration register read/write mask of bits in global status register and for global error bit table 24. rom memory map address name access content 00h id header read only 4300h (assp st_spi) 01h version read only 0300h 02h product code 1 read only 4300h (67 st_spi) 03h product code 2 read only 4800h (h st_spi) 3eh spi-frame id read only 0200h spi-frame-id register (st_spi)
spi - control and status registers l99dz70xp 34/47 doc id 15162 rev 4 5 spi - control and status registers 5.1 control register 0 table 25. control register 0 (read/write) bit name comment 15 out1 ? hs on/off if a bit is set the selected output driver is switched on. if the corresponding pwm enable bit is set the driver is only activated if pwm1 (pwm2) input signal is high. the outputs of out1-out6 are half bridges. if the bits of hs- and ls-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from vs to gnd. 14 out1 ? ls on/off 13 out2 ? hs on/off 12 out2 ? ls on/off 11 out3 ? hs on/off 10 out3 ? ls on/off 9 out4 ? hs on/off 8 out4 ? ls on/off 7 out5 ? hs on/off 6 out5 ? ls on/off 5 out6 ? hs on/off 4 out6 ? ls on/off 30 reserved (has to be set to '0') 20 10 0 enable bit if enable bit is set the device will be switched in active mode. if enable bit is cleared, the device enters standby mode and all bits are cleared.
l99dz70xp spi - control and status registers doc id 15162 rev 4 35/47 5.2 control register 1 table 26. control register 1 (read/write) bit name comment 15 out7 ? hs1 on/off out 7/8 14 out7 ? hs2 on/off hs1 hs2 mode 11 off 13 out8 ? hs1 on/off 1 0 low on-resistance 0 1 high on-resistance 12 out8 ? hs2 on/off 00 off 11 out9 ? hs on/off if a bit is set, the selected output driver is switched on. if the corresponding pwm enable bit is set the driver is only activated if pwm1 (pwm2) input signal is high. the outputs of out1-out6 are half bridges. if the bits of hs- and ls-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from vs to gnd. 10 out10 ? hs on/off 9 out11 ? hs on/off 8 ecv ? ls on/off 7 ec bit 5 reference value for difference voltage amplifier at pin ecv is binary coded. full scale value is set in control register 2. if all ec bits are set to zero the reference value is 0v. for fast discharge a lowside switch can be activated at pin ecv, if the ecv ? ls on/off bit is set to '1'.. 6 ec bit 4 5 ec bit 3 4 ec bit 2 3 ec bit 1 2 ec bit 0 1 ec switch in case this bit is set to 1, the electrochrome control is active and enables the driver at pin ecdr for the external mos transistor. the bit switches the highside out10 directly on, ignoring bit 10 in control register 1. if the drain of the external mos transistor is connected to out10, the current from supply vs to the load at ecv can be monitored. 0 0 reserved (has to be set to '0')
spi - control and status registers l99dz70xp 36/47 doc id 15162 rev 4 5.3 control register 2 table 27. control register 2 (read/write) bit name comment 15 out1 ? ocr enable in case of an over-current event the over-current status bit (status register 0) is set and the output is switched off. if the over-current recovery enable bit (ocr) is set, the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle (bit 5 of control register 3). depending on occurrence of over-current event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. the ecv-ocr enable bit is disabled in electrochrome mode (bit1=1 control register 1). 14 out2 ? ocr enable 13 out3 ? ocr enable 12 out4 ? ocr enable 11 out5 ? ocr enable 10 out6 ? ocr enable 9 ecv ? ocr enable 8 0 reserved (has to be set to '0') 7 out1 pwm1 enable if the pwm1/2 enable bit is set and the output is enabled (control register 0 or 1) the output is switched on if pwm1/2 input is high and switched off if pwm1/2 input is low. out5, 8 and out10 are controlled by pwm2 input, all other outputs are controlled by pwm1 input. 6 out2 pwm1 enable 5 out3 pwm1 enable 4 out4 pwm1 enable 3 out5 pwm2 enable 2 out6 pwm1 enable 1 ecv pwm1 enable 0 ecv-low voltage the maximum ecv voltage in electrochrome mode is 1.5v. it corresponds to the full scale range of the digital to analog converter dac set by the bits 7 to 2 of control register 1. if the ecv_low voltage bit is set to '0', the maximum voltage is limited to 1.2v without changing the resolution of the dac. this is the default mode.
l99dz70xp spi - control and status registers doc id 15162 rev 4 37/47 5.4 control register 3 table 28. control register 3 (read/write) bit name comment 15 out7-ocr enable in case of an over-current event the over-current status bit (status register 1) is set and the output is switched off. if the over-current recovery enable bit (ocr) is set the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle (bit 5). depending on the occurrence of the over-current event and the internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. 14 out8-ocr enable 13 out9-ocr enable 12 out10-ocr enable 11 out11-ocr enable 10 out7 pwm1 enable if the pwm1/2 enable bit is set and the output is enabled (control register 0 or 1) the output is switched on if pwm1/2 input is high and switched off if pwm1/2 input is low. out5, 8 and out10 are controlled by pwm2 input all other outputs are controlled by pwm1 input. 9 out8 pwm2 enable 8 out9 pwm1 enable 7 out10 pwm2 enable 6 out11 pwm1 enable 5 ocr frequency 0: 1.7 khz 1: 3 khz this bit defines in combination with the over-current recovery bit (input register 1) the over-current recovery frequency of an activated driver. 4 ov/uvr disable if this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs. 3 cm select bit 3 depending on combination of bit 3 to 0 the current image of the selected highside output outn will be multiplexed to the cm/pwm2 output (see table below). other combinations deactivate the current monitor. bit 3 bit 2 bit 1 bit 0 current image of 00 0 0 out1 2 cm select bit 2 00 0 1 out2 00 1 0 out3 00 1 1 out4 01 0 0 out5 1 cm select bit 1 01 0 1 out6 01 1 0 out7 01 1 1 out8 10 0 0 out9 0 cm select bit 0 10 0 1 out10 10 1 0 out11
spi - control and status registers l99dz70xp 38/47 doc id 15162 rev 4 5.5 status register 0 table 29. status register 0 (read) bit name comment 15 out1 ? hs oc in case of an over-current event the corresponding status bit is set and the output driver is disabled. if the over-current recovery enable bit is set the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle. if the over-current recovery bit is not set, the micro controller has to clear the over-current bit to reactivate the output driver. 14 out1 ? ls oc 13 out2 ? hs oc 12 out2 ? ls oc 11 out3 ? hs oc 10 out3 ? ls oc 9 out4 ? hs oc 8 out4 ? ls oc 7 out5 ? hs oc 6 out5 ? ls oc 5 out6 ? hs oc 4 out6 ? ls oc 30 reserved 20 10 00
l99dz70xp spi - control and status registers doc id 15162 rev 4 39/47 5.6 status register 1 table 30. status register 1 (read) bit name comment 15 out1 ? hs uc maskable by the configuration register 14 out1 ? ls uc 13 out2 ? hs uc the open load detection monitors the load current in each activated output stage. if the load current is below the under-current detection threshold for at least 1 ms (t dol ) , the corresponding under-current bit uc is set. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 12 out2 ? ls uc 11 out3 ? hs uc 10 out3 ? ls uc 9 out4 ? hs uc 8 out4 ? ls uc 7 out5 ? hs uc 6 out5 ? ls uc 5 out6 ? hs uc 4 out6 ? ls uc 30 reserved 20 10 00
spi - control and status registers l99dz70xp 40/47 doc id 15162 rev 4 5.7 status register 2 table 31. status register 2 (read) bit name comment 15 out7 ? oc in case of an over-current event the corresponding status bit oc is set and the output driver is disabled. if the over-current recovery enable bit is set the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle. if the over-current recovery bit is not set the micro controller has to clear the over-current bit to reactivate the output driver. the open load detection monitors the load current in each activated output stage. if the load current is below the under-current detection threshold for at least 1 ms (t dol ) the corresponding under-current bit uc is set. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 14 out7 ? uc 13 out8 ? oc 12 out8 ? uc 11 out9 ? oc 10 out9 ? uc 9 out10 ? oc 8 out10 ? uc 7out11 ? oc 6 out11 ? uc 5ecv ? oc 4 ecv ? uc 3 vs under-voltage in case of an over-voltage or under-voltage event the corresponding bit is set and the outputs are deactivated. if vs voltage recovers to normal operating conditions outputs are reactivated automatically (if bit 4 of control register 3 is not set). 2 vs over-voltage 1 ecv voltage not reached two comparators monitor the voltage at pin ecv in electrocrome mode. if this voltage is below / above the programmed target these bits signal the difference after at least 32 s. the bits are not latched and may toggle after at least 32 s, if the ecv voltage has not yet reached the target. they are not assigned to the global error flag. 0 ecv voltage too high
l99dz70xp spi - control and status registers doc id 15162 rev 4 41/47 5.8 configuration register table 32. configuration register (read/write) bit name comment 15 0 reserved (has to be set to '0') 14 0 13 0 12 0 11 0 10 0 90 80 70 60 5 mask for bit 15 of status reg. 1 openload event (under-current status bit of out1 hs) is not considered in openload bit 1 of global status register. 4 mask for bit 14 of status reg. 1 openload event (under-current status bit of out1 ls) is not considered in openload bit 1 of global status register. 3 mask for bit 3 of global status reg. temperature warning event is not considered in the 'global error flag'. 2 0 reserved (has to be set to '0') 1 mask for bit 1 of global status reg. openload event (under-current status bit of outn) is not considered in the 'global error flag'. 0 0 reserved (has to be set to '0')
packages thermal data l99dz70xp 42/47 doc id 15162 rev 4 6 packages thermal data figure 12. packages thermal data
l99dz70xp package and packing information doc id 15162 rev 4 43/47 7 package and packing information 7.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.2 powersso-36 package information figure 13. powersso-36 package dimensions
package and packing information l99dz70xp 44/47 doc id 15162 rev 4 table 33. powersso-36 mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.1 b0.18 - 0.36 c0.23-0.32 d (1) 1. ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side (0.006?). 10.10 - 10.50 e 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h10.1 - 10.5 h- -0.4 k0-8 l0.55 - 0.85 m-4.3- n - - 10 o-1.2- q-0.8- s-2.9- t-3.65- u-1- x 4.3 - 5.2 y 6.9 - 7.5
l99dz70xp package and packing information doc id 15162 rev 4 45/47 7.3 powersso-36 packing information figure 14. powersso-36 tube shipment (no suffix) figure 15. powersso-36 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base qty 49 bulk qty 1225 tube length (0.5) 532 a 3.5 b 13.8 c (0.1) 0.6 a c b base qty 1000 bulk qty 1000 a (max) 330 b (min) 1.5 c (0.2) 13 f 20.2 g (+2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 (0.1) 4 component spacing p 12 hole diameter d (0.05) 1.55 hole diameter d1 (min) 1.5 hole position f (0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 (0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets sealed with cover tape. user direction of feed
revision history l99dz70xp 46/47 doc id 15162 rev 4 8 revision history table 34. document revision history date revision description of changes 12-nov-2008 1 initial release. 02-jul-2009 2 table 33: powersso-36 mechanical data : ? deleted a (min) value ? changed a (max) value from 2.50 to 2.45 ? changed a2 (max) value from 2.40 to 2.35 ? changed l (max) value from 0.90 to 0.85 19-nov-2010 3 updated figure 1: block diagram 22-sep-2013 4 updated disclaimer.
l99dz70xp doc id 15162 rev 4 47/47 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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